Enhancement-mode III-nitride devices

ABSTRACT

A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.

CROSS-REFERENCE TO RELATED APPLICATION

This is a divisional application of U.S. application Ser. No. 13/799,989, filed on Mar. 13, 2013, the disclosure of which is hereby incorporated by reference in its entirety.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

This invention was made with Government support awarded by ARPA-E [Award #DE-AR0000212]. The Government has certain rights in this invention, including the right to revoke or modify the license to manufacture if the recipient is unable to expeditiously realize practical applications.

TECHNICAL FIELD

This invention relates to semiconductor electronic devices, specifically devices with electrodes connected to field plates.

BACKGROUND

Most power semiconductor devices such as high-voltage P-I-N diodes and power transistors such as power MOSFETs and Insulated Gate Bipolar Transistors (IGBT) have been typically fabricated with silicon (Si) semiconductor materials. More recently, silicon carbide (SiC) power devices have been used due to their superior properties. III-Nitride (III-N) semiconductor devices are emerging as an attractive candidate to carry large currents and support high voltages, and provide very low on resistance, high voltage operation, and fast switching times. As used herein, the terms III-N or III-Nitride materials, layers, devices, etc., refer to a material or device comprised of a compound semiconductor material according to the stoichiometric formula B_(w)Al_(x)In_(y)Ga_(z)N, where w+x+y+z is about 1.

Examples of III-N high electron mobility transistors (HEMTs) of the prior art are shown in FIGS. 1 and 2. The III-N HEMT of FIG. 1 includes a substrate 10, a III-N channel layer 11, such as a layer of GaN, atop the substrate, and a III-N barrier layer 12, such as a layer of Al_(x)Ga_(1-x)N, atop the channel layer. A two-dimensional electron gas (2DEG) channel 19 is induced in the channel layer 11 near the interface between the channel layer 11 and the barrier layer 12. Source and drain contacts 14 and 15, respectively, form ohmic contacts to the 2DEG channel. Gate contact 16 modulates the portion of the 2DEG in the gate region, i.e., directly beneath gate contact 16.

Field plates are commonly used in III-N devices to shape the electric field in the high-field region of the device in such a way that reduces the peak electric field and increases the device breakdown voltage, thereby allowing for higher voltage operation. An example of a field plated III-N HEMT of the prior art is shown in FIG. 2. In addition to the layers included in the device of FIG. 1, the device in FIG. 2 includes a field plate 18 which is connected to gate 16, and an insulator layer 13, such as a layer of SiN, is between the field plate 18 and the III-N barrier layer 12. Field plate 18 can include or be formed of the same material as gate 16. Insulator layer 13 can act as a surface passivation layer, preventing or suppressing voltage fluctuations at the surface of the III-N material adjacent to insulator layer 13.

Slant field plates have been shown to be particularly effective in reducing the peak electric field and increasing the breakdown voltage in III-N devices. A prior art III-N device similar to that of FIG. 2, but with a slant field plate 24, is shown in FIG. 3. In this device, gate 16 (i.e., the portion of electrode 29 that is between the vertical dashed lines) and slant field plate 24 are formed of a single electrode 29. Electrode-defining layer 23 is an insulating layer, such as SiN, that contains a recess which defines at least in part the shape of electrode 29. Electrode-defining layer 23 can also act as a surface passivation layer, preventing or suppressing voltage fluctuations at the surface of the III-N material adjacent to electrode-defining layer 23. Gate 16 and slant field plate 24 in this device can be formed by first depositing electrode-defining layer 23 over the entire surface of III-N barrier layer 12, then etching a recess through the electrode-defining layer 23 in the region containing gate 16, the recess including a slanted sidewall 25, and finally depositing electrode 29 at least in the recess and over the slanted sidewall 25.

Slant field plates, such as field plate 24 in FIG. 3, tend to spread the electric fields in the device over a larger volume as compared to conventional field plates, such as field plate 18 in FIG. 2, which do not include a slanted portion. Hence, slant field plates tend to be more effective at reducing the peak electric field in the underlying device, thereby allowing for larger operating and breakdown voltages.

The III-N HEMTs shown in FIGS. 1-3 are depletion-mode (i.e., D-mode), or normally-on devices. That is, they are in the ON (conductive) state when 0V is applied to the gate relative to the source and a positive voltage is applied to the drain relative to the source. In order to turn the devices OFF such that they are in a non-conductive state, a sufficiently negative voltage must be applied to the gate relative to the source. In many applications, it is desirable to utilize enhancement-mode (or E-mode) devices, i.e., devices with a positive threshold voltage, as this can simplify the form of the signals applied by the gate-drive circuit to the device and can prevent accidental turn on of the device in case of device or circuit failure.

Reliable fabrication and manufacturing of high-voltage III-N E-mode devices has thus far proven to be very difficult. One prior art alternative to a single high-voltage III-N E-mode device is to combine a high-voltage III-N D-mode device with a low-voltage silicon-based E-mode device in the configuration of FIG. 4 to form a hybrid device, which in many cases achieves the same or similar output characteristics as a single high-voltage E-mode device. The hybrid device of FIG. 4 includes a high-voltage III-N D-mode transistor 5 and a low-voltage silicon-based E-mode transistor 4. Node 1 serves as the source of the hybrid device, node 2 serves as the gate of the hybrid device, and node 3 serves as the drain of the hybrid device. The source electrode of the low-voltage E-mode transistor 4 and the gate electrode of the high-voltage D-mode transistor 5 are both electrically connected to the source node 1. The gate electrode of the low-voltage E-mode transistor 4 is electrically connected to the gate node 2. The drain electrode of the high-voltage D-mode transistor 5 is electrically connected to the drain node 3. The source electrode of the high-voltage D-mode transistor 5 is electrically connected to the drain electrode of the low-voltage E-mode transistor 4. When gate node 2 is biased relative to source node 1 at a voltage higher than the threshold voltage of E-mode transistor 4, the hybrid device is in the ON state, and conducts current between source and drain nodes 1 and 3, respectively, when a positive voltage is applied to the drain node 3 relative to the source node 1. When gate node 2 is biased relative to source node 1 at zero volts or at another voltage which is lower than the threshold voltage of E-mode transistor 4, the hybrid device is in the OFF state. In the OFF state, the hybrid device does not conduct substantial current between source and drain nodes 1 and 3, respectively, when a positive voltage is applied to the drain node 3 relative to the source node 1. In this state, the hybrid device is capable of supporting any drain-source voltages which are less than or equal to the breakdown voltage of the high-voltage D-mode transistor 5.

SUMMARY

In a first aspect, a III-N device is described. The III-N device comprises a III-N enhancement-mode transistor including a source contact and a first gate, the first gate being on a gate insulator, and a III-N depletion-mode transistor including a drain contact. The III-N device also includes a III-N structure including a conductive channel, where a first portion of the conductive channel serves as a device channel of the III-N enhancement-mode transistor, and a second portion of the conductive channel serves as a device channel of the III-N depletion-mode transistor. The III-N device further includes an insulator layer over the III-N structure, where a first recess is formed through the insulator layer in a gate region of the III-N enhancement-mode transistor, and the gate insulator and the first gate are at least partially in the recess. The III-N device also includes an electrode-defining layer having a thickness, the electrode-defining layer being over the insulator layer, with a second recess being formed in the electrode-defining layer in a gate region of the III-N depletion-mode transistor, the second recess including a sidewall proximal to the drain contact. The III-N device further includes an electrode in the second recess, the electrode including a second gate of the III-N depletion-mode transistor and an extending portion, the second gate being in a gate region of the III-N depletion-mode transistor, and the extending portion being at least partially over the sidewall. Additionally, the electrode is electrically connected to the source contact.

In a second aspect, a III-N enhancement-mode transistor is described. The transistor comprises a III-N structure including a conductive channel therein, a source contact and a drain contact, the source and drain contacts electrically contacting the conductive channel, and a gate electrode positioned between the source and drain contacts. The transistor also includes an insulator layer over the III-N structure, where a recess is formed through the insulator layer in a gate region of the III-N enhancement-mode transistor, and the gate electrode is at least partially in the recess. The transistor further includes a field plate having a portion that is between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact, and a separation between the conductive channel and the extending portion of the gate electrode is greater than a separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.

In a third aspect, another enhancement-mode transistor is described. The transistor comprises a semiconductor material structure including a conductive channel therein, and a source contact and a drain contact, with the source and drain contacts electrically contacting the conductive channel. The transistor also includes a gate electrode positioned between the source and drain contacts, a field plate that is electrically connected to the source contact, and a diode, with a first side of the diode electrically connected to the field plate.

In a fourth aspect, a half bridge is described. The half bridge comprises a III-N structure including a conductive channel therein, and a first gate electrode and a second gate electrode, the first and second gate electrodes being on the III-N structure. The half bridge also includes a first source contact and a drain contact, the first source contact and the drain contact electrically contacting the conductive channel, and the first and second gate electrodes are both between the first source contact and the drain contact. The half bridge further includes a second source contact, the second source contact including a first portion electrically contacting the conductive channel, wherein the first portion of the second source contact is between the first gate electrode and the second gate electrode. Additionally, the first source contact is part of a first electrode and the second source contact is part of a second electrode, the first electrode including a portion which is between the first gate electrode and the second source contact, and the second electrode including a portion that is between the second gate electrode and the drain contact.

In a fifth aspect, a bidirectional switch is described. The bidirectional switch comprises a III-N structure including a conductive channel therein, and a first gate electrode and a second gate electrode, the first and second gate electrodes being on the III-N structure. The bidirectional switch also includes a first source contact and a second source contact, the first source and second source contacts electrically contacting the conductive channel, where the first and second gate electrodes are each between the first and second source contacts. Furthermore, the first source contact is part of a first electrode and the second source contact is part of a second electrode, the first electrode including a first portion which is between the first and second gate electrodes, and the second electrode including a second portion that is between the first and second gate electrodes.

Each of the devices, transistors, half bridges, and bidirectional switches described herein can include one or more of the following features. A portion of the second recess distal from the III-N structure can have a first width and a portion of the second recess proximal to the III-N structure can have a second width, the first width being larger than the second width. A breakdown voltage of the III-N depletion-mode transistor can be at least 3 times a breakdown voltage of the III-N enhancement-mode transistor. The device can be configured to function as an enhancement-mode transistor having a breakdown voltage which is at least 3 times the breakdown voltage of the III-N enhancement-mode transistor. The electrode-defining layer can be over both the device channel of the III-N enhancement-mode transistor and the device channel of the III-N depletion-mode transistor. The first gate can include an extending portion that is outside the first recess and extends towards the drain contact. A separation between the conductive channel and the extending portion of the first gate can be greater than a separation between the conductive channel and the second gate. The first recess can extend into the III-N structure. The first recess can extend through the conductive channel.

The III-N structure can comprise a first III-N layer and a second III-N layer, wherein the conductive channel is a 2DEG channel induced in the first III-N layer adjacent to the second III-N layer as a result of a compositional difference between the first III-N layer and the second III-N layer. The second recess can extend completely through the thickness of the electrode-defining layer. The electrode-defining layer can comprise SiN_(x). The device can further include an additional dielectric layer between the insulator layer and the electrode-defining layer. The additional dielectric layer can comprise AlN, and the insulator layer can comprise SiN. The sidewall can include a plurality of steps. The device can further comprise an additional contact between the first gate and the second gate, the additional contact contacting the conductive channel. The device can further comprise a current-carrying component, wherein a first side of the current-carrying component is electrically connected to the source contact and a second side of the current-carrying component is electrically connected to the additional contact. The current-carrying component can comprise a diode, with the first side of the current-carrying component being an anode, and the second side of the current-carrying component being a cathode. The current-carrying component can comprise a resistor. The III-N enhancement-mode transistor can lack a drain contact, the III-N depletion-mode transistor can lack a source contact, and the III-N enhancement-mode transistor and III-N depletion-mode transistor can share a common drift region between the first gate and the second gate.

The device can further comprise an additional contact between the gate electrode and the drain electrode. The additional contact can electrically contact the conductive channel. The device can further comprise a diode, wherein a first side of the diode is electrically connected to the field plate and a second side of the diode is electrically connected to the additional contact. The first side of the diode can be an anode and the second side of the diode can be a cathode. The semiconductor material structure can comprise one or more III-Nitride layers, with the conductive channel in the one or more III-Nitride layers. The device can further comprise an additional contact between the gate electrode and the drain electrode. The additional contact can electrically contact the conductive channel. A second side of the diode can be electrically connected to the additional contact. The gate electrode can include a main gate portion and an extending portion, the extending portion extending from the main gate portion towards the drain contact, the field plate can include a portion which is between the extending portion and the drain contact, and a separation between the conductive channel and the extending portion of the gate electrode can be greater than a separation between the conductive channel and the portion of the field plate which is between the extending portion and the drain contact.

The device or half bridge can further comprise an additional contact between the first gate electrode and the drain contact, as well as a diode having an anode and a cathode, wherein the anode is electrically connected to the first electrode or to the second electrode, and the cathode is electrically connected to the additional contact. The additional contact can electrically contact the conductive channel. The first gate can be part of a first III-N switch and the second gate can be part of a second III-N switch. The half bridge or device can further comprise an additional contact between the first gate electrode and the second source contact, as well as a diode having an anode and a cathode, wherein the anode is electrically connected to the first electrode and the cathode is electrically connected to the additional contact. A reverse bias breakdown voltage of the diode can be smaller than a breakdown voltage of the first III-N switch. The reverse bias breakdown voltage of the diode can be less than 0.5 times the breakdown voltage of the first III-N switch. The second electrode can be configured to operate as a drain of the first III-N switch.

The first gate electrode can include a main gate portion and an extending portion, the extending portion can extend from the main gate portion towards the drain contact, and a separation between the conductive channel and the extending portion of the first gate electrode can be greater than a separation between the conductive channel and the portion of the first electrode which is between the first gate electrode and the second source contact. The half bridge can further comprise an insulating material over the III-N structure, the insulating material including a first recess and a second recess, wherein the portion of the first electrode which is between the first gate electrode and the second source contact is in the first recess, and the portion of the second electrode which is between the second gate electrode and the drain contact is in the second recess.

The bidirectional switch or device can further comprise a first additional contact between the first gate electrode and the second gate electrode, as well as a first diode having an first anode and a first cathode, wherein the first anode is electrically connected to the first electrode and the first cathode is electrically connected to the first additional contact. The additional contact can electrically contact the conductive channel. The bidirectional switch or device can further comprise a second additional contact between the first gate and second gate electrodes and a second diode having a second anode and a second cathode, wherein the second anode is electrically connected to the second electrode and the second cathode is electrically connected to the second additional contact. A reverse bias breakdown voltage of the diode can be smaller than a breakdown voltage of the device or bidirectional switch. The reverse bias breakdown voltage of the diode can be less than 0.3 times the breakdown voltage of the device or bidirectional switch.

The first gate electrode can include a main gate portion and an extending portion, the extending portion extending from the main gate portion towards the second gate electrode, wherein a separation between the conductive channel and the extending portion of the first gate electrode is greater than a separation between the conductive channel and the first portion of the first electrode. The bidirectional switch or device can further comprise an insulating material over the III-N structure, the insulating material including a first recess and a second recess, wherein the first portion of the first electrode is in the first recess, and the second portion of the second electrode is in the second recess.

III-N devices which can be fabricated reproducibly, can support high voltages with low leakage, and at the same time can exhibit low on-resistance and high breakdown voltage, are described. Methods of forming the devices are also described. The III-N devices described herein can be transistors, half bridges, and/or bidirectional switches, and can be high-voltage devices suitable for high voltage applications. The details of one or more implementations of the invention are set forth in the accompanying drawings and description below. Other features and advantages of the invention will be apparent from the description and drawings, and from the claims.

DESCRIPTION OF DRAWINGS

FIGS. 1-3 are cross-sectional views of III-N HEMT devices of the prior art.

FIG. 4 is a circuit representation of a prior art hybrid enhancement-mode device.

FIG. 5A is a cross-sectional view of an implementation of a III-N device.

FIG. 5B is a circuit representation of the device of FIG. 5A.

FIGS. 6-8 are cross-sectional views of other implementations of III-N devices.

FIG. 9A is a plan view of yet another implementation of a III-N device.

FIG. 9B is a cross-sectional view along dashed line 8 of the III-N device of FIG. 9A.

FIG. 9C is a cross-sectional view along dashed line 9 of the III-N device of FIG. 9A.

FIGS. 10A and 10B are cross-sectional and plan views, respectively, of still another implementation of a III-N device.

FIG. 10C is a plan view of yet another implementation of a III-N device.

FIG. 10D is a cross-sectional view of yet another implementation of a III-N device.

FIGS. 11-20 illustrate a method of fabricating the III-N device of FIG. 8.

FIG. 21A is a cross-sectional view of an implementation of a half bridge.

FIG. 21B is a circuit schematic of the half bridge of FIG. 21A connected to an inductive load.

FIGS. 22-24 are cross-sectional views of implementations of bidirectional switches.

Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

Devices based on III-N heterostructures are described. The III-N devices are designed to operate as enhancement-mode transistor devices. The III-N devices described herein can be high-voltage devices suitable for high voltage applications. In such a high-voltage device, when the device is biased off (i.e., the voltage on the gate relative to the source is less than the device threshold voltage), it is at least capable of supporting all source-drain voltages less than or equal to the high-voltage in the application in which the device is used, which for example may be 100V, 300V, 600V, 1200V, 1700V, or higher. When the high voltage device is biased on (i.e., the voltage on the gate relative to the source is greater than the device threshold voltage), it is able to conduct substantial current with a low on-voltage. The maximum allowable on-voltage is the maximum voltage that can be sustained in the application in which the device is used.

Implementations of the device described herein are illustrated in FIGS. 5-23. FIG. 5A is a cross-sectional view of the device, and FIG. 5B is a circuit schematic diagram of the device of FIG. 5A. Referring to FIGS. 5A and 5B, a hybrid enhancement-mode electronic device 40 is formed of a III-Nitride low-voltage enhancement-mode transistor 41 and a III-Nitride high-voltage depletion-mode transistor 42. Transistors 41 and 42 are formed on a common set of III-Nitride layers 11 and 12, such that the entire hybrid device 40 is integrated onto a single chip. As shown in FIG. 5A, both devices 41 and 42 include a device channel 19 which is in the common set of III-N material layers 11 and 12. The hybrid device 40 further includes a substrate 10 (although the substrate is optional), which can for example be silicon, GaN, silicon carbide, AlN, or sapphire, as well as a first III-N layer 11 on top of the substrate, and a second III-N layer 12 on top of the first III-N layer. III-N layers 11 and 12 have different compositions from one another, the compositions selected such that a two-dimensional electron gas (2DEG) 19 (illustrated by a dashed line), i.e., a conductive channel, is induced in the first III-N layer 11 near the interface between the first and second III-N layers 11 and 12, respectively. The hybrid device 40 further includes an insulator layer 22, such as SiN, on the second III-N layer 12. Insulator layer 22 can serve as a passivation layer for the III-Nitride material layers 11 and 12, as well as serving as a gate insulator layer for depletion-mode transistor 42, as further described below.

Enhancement-mode transistor 41 additionally includes source and drain contacts 34 and 35, respectively, which form ohmic contacts to the 2DEG 19, and a gate contact 38 formed on a gate insulator 37. The gate of the enhancement-mode transistor 41 is formed as follows. After depositing insulator layer 22 over III-N layer 12, a recess is etched through insulator layer 22 and into the III-N materials in the gate region 61 of the enhancement-mode transistor 41. As shown in FIG. 5A, the recess can extend through the 2DEG channel 19. Alternatively, the recess may extend partially through III-N layer 12 without extending into III-N layer 11, such that the recess does not extend all the way through the 2DEG channel 19 (not shown). The recess is sufficiently deep to ensure that the gate region 61 of enhancement-mode transistor 41 is not conductive when 0V is applied to the gate contact 38 relative to the source contact 34, but is readily conductive when a sufficiently positive voltage is applied to the gate contact 38 relative to the source contact 34. Although the sidewalls of the recess are shown to be substantially vertical, they could alternatively be formed as slanted sidewalls (not shown).

A gate insulator 37 is then conformally deposited in the gate region 61 and over the entire upper surface of insulator layer 22. Gate insulator 37 can, for example, be formed of or include aluminum oxide, silicon dioxide, or another wide bandgap insulator. Next, the gate contact 38 is deposited conformally over gate insulator 37 in the recess in gate region 61. The gate contact 38 includes extending portions 31 and 32 that extend towards the source 34 and drain 35 contacts, respectively. The extending portions 31 and 32 are in the source and drain access regions 62 and 63, respectively, of the enhancement-mode transistor 41, and are over the upper surface of both gate insulator 37 and insulator layer 22. Extending portion 32 functions as a field plate for the enhancement-mode transistor 41. In implementations where the sidewalls of the recess in which layers 37 and 38 are deposited are slanted, extending portion 32 functions as a slant field plate, which may improve device performance. Finally, the gate contact 38 is used as an etch mask to etch gate insulator 37, such that gate insulator 37 remains directly beneath gate contact 38 but is etched away everywhere else.

Referring now to the high-voltage depletion-mode transistor 42 of hybrid device 40, depletion-mode transistor 42 includes source and drain contacts 44 and 45, respectively, which form ohmic contacts to the 2DEG 19. Depletion-mode transistor 42 also includes an electrode 49 which is deposited in a recess 17 in an electrode-defining layer 33 which is formed over the III-N material layers 11 and 12. The recess 17 can extend through the entire thickness of the electrode-defining layer 33, as shown in FIG. 5A. Alternatively, the recess 17 may only extend partially through the electrode-defining layer 33 (not shown). The width at the top of the recess 17 is greater than the width at the bottom of the recess 17. The electrode 49 is deposited conformally in the recess 17 in the electrode-defining layer 33 with extending portions 46 and 47 over sidewalls of the recess. Hence, the profiles of the extending portions are at least partially determined by the profiles of the corresponding sidewalls.

The electrode-defining layer 33 is typically between about 0.1 microns and 5 microns thick, such as about 0.85 microns thick. The electrode-defining layer 33 can have a composition that is substantially uniform throughout. The electrode-defining layer 33 is formed of an insulator, such as silicon nitride (SiN_(x)).

As described above, electrode 49 is formed in the recess 17. In the implementation shown in FIG. 5A, the electrode 49 conformally covers the entire exposed surface in the recess, although in some implementations the electrode 49 only covers a portion of the exposed surface in the recess (not shown), as further described below. The portion of electrode 49 in gate region 51 is the gate 48 of the device. Electrode 49 further includes a first extending portion 47, which is over a portion of the electrode-defining layer 33 in the drain access region 53, and a second extending portion 46, which is over a portion of the electrode-defining layer 33 in the source access region 52. The first extending portion 47 functions as a field plate, reducing the peak electric field in the depletion-mode transistor 42 when the hybrid device 40 is biased in the OFF state (i.e., with the voltage of gate node 2 relative to source node 1 lower than the device threshold voltage) with a large drain-source voltage. The second extending portion 46 is included to ensure that the electrode 49 extends towards the source contact 44 at least beyond the source-side edge of the gate region 51 in case of misalignment of the gate electrode 49 to the recess during device fabrication. Although the second extending portion 46 is shown to extend all the way over the source-side sidewall of the recess 17, in some implementation, it may only extend partially up the sidewall (not shown). Having the second extending portion 46 extend partially up the sidewall may reduce capacitances in the device, thereby improving device performance.

Source and drain contacts 44 and 45, respectively, are on opposite sides of the gate 48. The depletion-mode transistor 42 also includes a gate region 51, in which the gate 48 is deposited, and source and drain access regions 52 and 53, respectively, on opposite sides of the gate region. The regions 56 of the device structure in which the source and drain contacts 44 and 45, respectively, are deposited are referred to as the device ohmic regions. The source access region 52 is between the source contact 44 and gate 48, and the drain access region 53 is between the drain contact 45 and gate 48.

The depletion-mode transistor 42 optionally includes an additional dielectric layer 21 between the electrode-defining layer 33 and the insulator layer 22. The additional dielectric layer 21, which can be formed of an insulator such as AlN, can serve as an etch stop layer during the formation of the recess 17, as further described below. As seen in FIG. 5A, the recess 17 may optionally extend through the entire thickness of the electrode-defining layer 33 and through the entire thickness of the additional dielectric layer 21. Gate 48 can then be formed on the insulator layer 22, such that insulator layer 22 is between the III-N materials and gate 48, such that insulator layer 22 serves as a gate insulator for the depletion-mode transistor 42. A gate insulator can help prevent gate leakage currents in the depletion-mode transistor 42. As also illustrated in FIG. 5A, the additional dielectric layer 21 and electrode-defining layer 33 may additionally be formed on or included in the enhancement-mode transistor 41.

In order for hybrid device 40 to operate as a high-voltage enhancement-mode device, transistors 41 and 42 are connected in the circuit configuration shown in FIG. 5B. That is, the source contact 44 of the depletion-mode transistor 42 is electrically connected to the drain contact 35 of the enhancement-mode transistor 41, and the gate 48 of the depletion-mode transistor 42 is electrically connected to the source contact 34 of the enhancement-mode transistor 41. As seen in FIG. 5A, such a configuration can be achieve by connecting contacts 35 to contact 44 via wire bond 36 and by connecting contact 34 to electrode 49 via wire bond 43. Alternatively, these connections can be formed in other ways, for example by running metal trace lines from contact 35 to contact 44 and from contact 34 to electrode 49.

In some implementations, in order to provide stability to the device and/or to improve reliability, a current-carrying component 39 (shown in FIG. 5A but not in FIG. 5B) can be connected between the source and drain contacts 34 and 35, respectively, of the enhancement-mode transistor 41. For example, if the device is to be used in applications where current flows through the device in both directions, for example as a switch in a bridge circuit, the enhancement-mode transistor 41 may be unstable in reverse conduction mode. In this case, stabilizing the device can be achieved by having current-carrying component 39 be a diode, where the anode of the diode is connected to source contact 34, and the cathode of the diode is connected to drain contact 35. When the device of FIG. 5A is operated in the off state with a positive voltage applied to drain contact 45 relative to source contact 34, the diode is reverse biased and blocks about the same voltage as enhancement-mode transistor 41. Hence, the diode does not need to be a high-voltage component. As such, hybrid device 40 can have a breakdown voltage that is at least 2 times or at least 3 times or at least 10 times that of the diode.

Alternatively, current-carrying component 39 could be included to allow off-state leakage currents in the enhancement-mode transistor 41 to be better matched to off-state leakage currents in the depletion-mode transistor 42. In this case, current-carrying component 39 can be a resistor, or a diode with an anode connected to drain contact 35 and a cathode connected to source contact 34. Or, current-carrying component 39 can be a combination of transistors and diodes, connected in parallel, series, or a combination of parallel and series connections.

Still referring to FIG. 5A, the separation between the extending portion 32 of the gate contact 38 of enhancement-mode transistor 41 and the device channel 19 is indicated by arrow 6, and the separation between the gate 48 of the depletion-mode transistor 42 and the device channel 19 is indicated by arrow 7. As illustrated, the separation indicated by arrow 6 can be made larger than the separation indicated by arrow 7. This relationship can also be maintained in all other device implementations described below. As compared to similar devices in which recess 17 does not extend as deep, such that the separation indicated by arrow 6 is smaller than the separation indicated by arrow 7, it has been found that the breakdown voltage of the device in FIG. 5A is increased and device stability is improved substantially, in particular during high voltage operation of the device. This result was unexpected. It is speculated that having gate 48 closer than extending portion 32 to the device channel 19 causes a larger percentage of the total voltage applied across hybrid device 40 to be supported by electric fields beneath extending portion 47 instead of by electric fields beneath or near extending portion 32. Stated differently, having gate 48 closer than extending portion 32 to the device channel 19 can cause the peak electric field in the device to be beneath or near extending portion 47 rather than beneath or near extending portion 32. This has the effect of reducing the ratio of voltage supported by the enhancement-mode transistor 41 to voltage supported by the depletion-mode transistor 42. Because depletion-mode transistor 42 is better equipped than enhancement-mode transistor 41 to support large voltages, such a configuration, along with the corresponding reduction in voltage across the enhancement-mode transistor 41, may provide more stability to the enhancement-mode transistor 41. Alternatively, a similar improvement in device stability could be achieved by utilizing insulating materials between portion 48 of electrode 49 and 2DEG 19 that have a larger average dielectric constant than that of the material between extending portion 32 and 2DEG 19. Specifically, if the separation indicated by arrow 6 divided by the average dielectric constant of the material directly between extending portion 32 and 2DEG 19 is greater than the separation indicated by arrow 6 divided by the average dielectric constant of the material directly between portion 48 and 2DEG 19, then a larger percentage of the total voltage applied across hybrid device 40 would be supported by electric fields beneath extending portion 47 instead of by electric fields beneath or near extending portion 32, and a similar improvement in device stability occurs.

As used herein, two or more contacts or other items such as conductive layers or components are said to be “electrically connected” if they are connected by a material which is sufficiently conducting to ensure that the electric potential at each of the contacts or other items is intended to be the same, i.e., is about the same, at all times under any bias conditions. As used herein, a “hybrid enhancement-mode electronic device or component” is an electronic device or component formed of a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor configured such that the component can operate similarly to a single high-voltage enhancement-mode transistor. That is, a hybrid enhancement-mode device or component includes at least 3 nodes having the following properties. When the first node (source node) and second node (gate node) are held at the same voltage, the hybrid enhancement-mode device or component can block a positive high voltage applied to the third node (drain node) relative to the source node. When the gate node is held at a sufficiently positive voltage relative to the source node, current passes from the source node to the drain node or from the drain node to the source node when a sufficiently positive voltage is applied to the source node relative to the drain node or to the drain node relative to the source node, respectively. As used herein, “blocking a voltage” refers to the ability of a transistor, device, or component to prevent significant current, such as current that is greater than 0.001 times the operating current during regular conduction, from flowing through the transistor, device, or component when a voltage is applied across the transistor, device, or component. In other words, while a transistor, device, or component is blocking a voltage that is applied across it, the total current passing through the transistor, device, or component will not be greater than 0.001 times the operating current during regular conduction. Devices with off-state currents which are larger than this value exhibit high loss and low efficiency, and are typically not suitable for many applications.

As used herein, a “high-voltage device”, such as a high-voltage switching transistor, is an electronic device which is optimized for high-voltage switching applications. That is, when the transistor is off, it is capable of blocking high voltages, such as about 300V or higher, about 600V or higher, or about 1200V or higher, and when the transistor is on, it has a sufficiently low on-resistance (R_(ON)) for the application in which it is used, i.e., it experiences sufficiently low conduction loss when a substantial current passes through the device. A high-voltage device can at least be capable of blocking a voltage equal to the high-voltage supply or the maximum voltage in the circuit for which it is used. A high-voltage device may be capable of blocking 300V, 600V, 1200V, or other suitable blocking voltage required by the application. In other words, a high-voltage device can block all voltages between 0V and at least V_(max), where V_(max) is the maximum voltage that can be supplied by the circuit or power supply, and V_(max) can for example be 300V, 600V, 1200V, or other suitable blocking voltage required by the application. In some implementations, a high-voltage device can block any voltage between 0V and at least 2*V_(max). As used herein, a “low-voltage device”, such as a low-voltage transistor, is an electronic device which is capable of blocking low voltages, such as between 0V and V_(low) (where V_(low) is less than V_(max)), but is not capable of blocking voltages higher than V_(low). In some implementations, V_(low) is equal to about |V_(th)|, about 2*|V_(th)|, about 3*|V_(th)|, or between about |V_(th)| and 3*|V_(th)|, where |V_(th)| is the absolute value of the threshold voltage of a high-voltage transistor contained within the circuit in which the low-voltage device is used. In other implementations, V_(low) is about 10V, about 20V, about 30V, about 40V, or between about 5V and 50V, such as between about 10V and 30V. In yet other implementations, V_(low) is less than about 0.5*V_(max), less than about 0.3*V_(max), less than about 0.1*V_(max), less than about 0.05*V_(max), or less than about 0.02*V_(max). In implementations described herein, high-voltage transistors which are connected or coupled to a low-voltage transistor can have breakdown voltages which are at least 3 times, at least 5 times, or at least 10 times the breakdown voltage of the low-voltage transistor.

Dispersion refers to a difference in observed current-voltage (I-V) characteristics when the device is operated under RF or switching conditions, as compared to when the device is operated under DC conditions. In III-N devices, effects such as dispersion are often caused by voltage fluctuations at the uppermost surface(s) of the III-N material layers, the result of charging of surface states during device operation. Accordingly, an insulating layer such as layer 22 in FIG. 5A can serve as a passivation layer, preventing or suppressing dispersion by preventing or suppressing voltage fluctuations at the uppermost III-N surface. In implementations where additional dielectric layer 21 is included between insulator layer 22 and electrode-defining layer 33, the combination of insulator layer 22, additional dielectric layer 21, and electrode-defining layer 33 maintain effective passivation of the uppermost III-N surface. In some cases, for example when the additional dielectric layer 21 is AlN, the layer 21 may need to be made thin enough, such as thinner than about 20 nm, thinner than about 10 nm, or thinner than about 5 nm, to ensure that effective passivation of the uppermost III-N surface is still maintained. Too thick an additional dielectric layer 21, such as greater than about 20 nm, can degrade the passivation effects of layers 22 and 33.

Referring again to FIG. 5A, because the drain contact 35 of the enhancement-mode transistor 41 is adjacent to the source contact 44 of the depletion-mode transistor 42, and the two contacts are electrically connected, the drain and source contacts 35 and 44, respectively, may be combined into a single contact 55. Such a configuration is shown in FIG. 6. Device 50 of FIG. 6 is the same as that in FIG. 5A, except that the drain and source contacts of transistors 41 and 42, respectively, have been combined into a single contact 55 (for clarity, some of the reference numerals from FIG. 5A are not shown in FIG. 6). In device 50 of FIG. 6, current-carrying component 39, when included, is connected to source contact 34 and contact 55 as shown. As compared to the device of FIG. 5A, the configuration shown in FIG. 6 can reduce the footprint of the device, thereby reducing costs, and can also simplify the fabrication process.

Referring now to FIGS. 5A and 6, because source contact 34 of the enhancement-mode transistor 41 is electrically connected to electrode 49 of the depletion-mode transistor 42 (by connection 43), source contact 34 and electrode 49 may be combined into a single electrode. Such a configuration is shown in FIG. 7. Device 60 of FIG. 7 is the same as device 50 of FIG. 6, except that the electrode-defining layer 33 (and optionally dielectric layer 21) is formed over contact 55. Furthermore, electrode 49 is extended to include portion 69, which extends all the way to and contacts source contact 34. Thus, source contact 34 and electrode 49 are provided as a single electrode 67. Although not shown in FIG. 7, a current-carrying component 39, such as that shown in FIGS. 5A and 6 and described previously, can also be between contacts 34 and 55, with one end of the current-carrying component electrically connected to contact 34 and the other end electrically connected to contact 55. Because contact 55 is beneath the single electrode 67, in order to access contact 55 so that a current-carrying component can be connected to it, the device 60 can include a region in which portion 69 is not included and the layers above contact 55 (i.e., layers 33 and 21) are removed. The gate 38 of the enhancement-mode transistor 41 may be similarly accessed.

For the devices of FIGS. 5-7, in implementations where current-carrying component 39 is not utilized, the contacts that form the drain of enhancement-mode transistor 41 and the source of depletion-mode transistor 42 (contacts 35 and 44 in FIG. 5A and contact 55 in FIGS. 5-6) are not used for any functional purpose during device operation. Hence, these contacts can be omitted. Consequently, in devices 40, 50, and 60 from FIGS. 5A, 6, and 7, respectively, the III-N enhancement-mode transistor 41 can lack a drain contact and the III-N depletion-mode transistor 42 can lack a source contact, in which case the III-N enhancement-mode transistor 41 and III-N depletion-mode transistor 42 share a common drift region between the gate contact 38 and gate 48.

FIG. 8 shows a cross-sectional view of another implementation of a III-Nitride device 70. Device 70 is a single enhancement-mode III-Nitride transistor. Electrode 77 of device 70 includes both the source contact 74 and a source-connected field plate 79. Similar to the gate electrode of the depletion-mode transistor in the implementations of FIGS. 5A, 6, and 7, field plate 79 is at least partially in a recess 17 formed in electrode-defining layer 33. Also similar to the implementations of FIGS. 5A, 6, and 7, device 70 additionally includes a substrate 10 (although the substrate is optional), a III-Nitride material structure including III-N layers 11 and 12 on the substrate 10, a 2DEG channel 19 in the III-Nitride material structure, an insulator layer 22 on the III-Nitride material structure, an additional dielectric layer 21 on the insulator layer 22, and an electrode-defining layer 33 on the additional dielectric layer 21. In some implementations, additional dielectric layer 21 and insulator layer 22 are optional and may be omitted (not shown). Device 70 also includes a drain contact 75, as well as a gate 88 formed on a gate insulator 87. Region 81, in which the gate 88 is deposited, is referred to as the gate region of the device. Regions 86, in which the source contact 74 and drain contact 75 are deposited, are referred to as the contact regions. Region 82, between the source contact region and the gate region, is referred to as the source access region. Region 83, between the drain contact region and the gate region, is referred to as the drain access region.

As in previous implementations, a recess is formed through the insulator layer 22 and optionally into the III-N material structure in the gate region 81 where gate 88 is formed, and gate insulator 87 and gate 88 are deposited in the recess. As seen in FIG. 8, the recess containing gate insulator 87 and gate 88 can be formed through the 2DEG channel 19. The recess can be formed at least deep enough that when 0V is applied to the gate 88 relative to the source contact 74, the device channel in the gate region 81 is depleted of charge, and the device is in the OFF state, but the device channel in the gate region becomes readily conductive when a sufficiently positive voltage is applied to the gate 88 relative to the source contact 74.

Similar to the case described for device 40 in FIG. 5A, in device 70 of FIG. 8, the extending portion 89 of the gate 88, which is over the upper surface of the III-N material structure (layers 11 and 12) and functions as a gate-connected field plate, can have a larger separation from the 2DEG channel 19 than the portion 78 of the source-connected field plate 79 which is at the bottom of the recess 17. Alternatively, the relationship between portion separation from the 2DEG 19 and average dielectric constant of the intermediary materials previously described with reference to device 40 of FIG. 5A may also be maintained in device 70.

The same may also be true for devices 80, 90, 90′, and 90″, which are illustrated in FIGS. 9A-9C, 10A-10B, 10C, and 10D, respectively, and are described in further detail below. As compared to similar devices in which recess 17 does not extend as deep, therefore resulting in a source-connected field plate which is everywhere further from the channel than the gate-connected field plate, or for which the ratio referenced above is not met, it has been found that the breakdown voltage of the device 70 in FIG. 8 is increased and device stability is improved substantially, in particular during high voltage operation of the device. This result was unexpected. It has been shown that in device 70, having portion 78 of field plate 79 closer than extending portion 89 to the device channel 19 causes a larger percentage of the total voltage applied across device 70 to be supported by electric fields beneath or near field plate 79 instead of by electric fields beneath or near extending portion 89. Stated differently, having portion 78 of field plate 79 closer than extending portion 89 to the device channel 19 can cause the peak electric field in the device to be beneath or near field plate 79 rather than beneath or near extending portion 89. The region beneath field plate 79 is better equipped to support large voltages with smaller peak electric fields than the region beneath or near the gate 88. Hence, such a configuration may provide more stability to device 70.

In the device 70 of FIG. 8, the source-connected field plate 79 is shown to run directly over the gate 88. That is, portion 71 of field plate 79 is directly over the gate 88 and is at least partially in the gate region 81 of the device. Although portion 71 could be over the gate 88 across the entire width of the gate, such a configuration could result in a large gate-to-source capacitance, which can degrade the device performance. Instead, portion 71 could be designed to only be over the gate over a portion of the gate width W_(gate).

Such a configuration is shown in device 80 of FIGS. 9A-9C, where FIG. 9A is a plan view (top view) of device 80, FIG. 9B is a cross-sectional view along dashed line 8 in FIG. 9A, and FIG. 9C is a cross-sectional view along dashed line 9 in FIG. 9A. As seen in FIG. 9A, portion 71 is formed of a plurality of strips, each of which passes over the gate 88 and connects source contact 74 to the remainder of electrode 79. However, in between each of the strips 71, material of electrode 77 is not included. As seen in FIG. 9C, electrode-defining layer 33 is between the strips 71 and gate 88, thereby allowing the strips 71 to run over the gate 88 without short-circuiting the gate 88 to the source contact 74. In some implementations, field plate 79 is directly over half the width of the gate or less.

For each of devices 70 and 80 in FIGS. 8 and 9, respectively, if the device is to be used in applications where current flows through the device in both directions, for example as a switch in a bridge circuit, the device may become unstable in reverse conduction mode (when the drain is at a lower voltage than the source and current flows through the device). In this case, stabilizing the device can be achieved by connecting a diode anti-parallel to the device (not shown), where the anode of the diode is connected to source contact 74, and the drain of the diode is connected to drain contact 75. For such a configuration, when device 70 or 80 is operated in reverse conduction mode with the gate biased below the device threshold voltage relative to the source, the reverse current flows through the diode rather than through the channel of the device. In this configuration, the reverse bias breakdown voltage of the diode as well as the breakdown voltage of the device 70 or 80 would need to be greater than the circuit high voltage.

FIGS. 10A and 10B show an alternative configuration for a device 90 in which a diode 99 having a substantially smaller reverse bias breakdown voltage than that of the device 90 is used to stabilize the device 90 during reverse conduction. FIG. 10A is a cross-sectional view of the device, while FIG. 10B is a plan view (top view). Device 90 of FIGS. 10A and 10B is similar to devices 70 and 80 of FIGS. 8 and 9, respectively, but further includes an electrode 85 contacting the 2DEG 19 between the gate 88 and the drain contact 75. Opposite ends of a diode 99 are connected to the electrode 85 and to electrode 77. As shown, the anode of the diode 99 is electrically connected to electrode 77, and the cathode is electrically connected to electrode 85. As also shown, the anode of diode 99 is electrically connected directly to the source-connected field plate 79 of electrode 77. Alternatively, the anode of diode 99 could be electrically connected directly to source contact 74 (not shown) or to the source bus which is connected to each of the source fingers in the device (not shown).

In the configuration shown in FIGS. 10A and 10B, when the device 90 is in reverse conduction mode, with the drain contact 75 biased at a slightly lower voltage than the source contact 74 and the gate 88 biased below the device threshold voltage relative to the source contact 74, current flows from the source contact 74 into the source-connected field plate 79, then through the diode 99 into electrode 85, and then through 2DEG 19 from electrode 85 to the drain contact 75. If the design of device 90 is modified such that the anode of diode 99 is electrically connected directly to source contact 74 or to the source bus, then in reverse conduction mode, current flows from the source contact 74 or from the source bus directly into the diode 99 without flowing into the source-connected field plate 79. When the device 90 is biased with a large positive voltage on the drain contact 75 relative to the source contact 74 and with the gate 88 below the device threshold voltage relative to the source contact 74, such that the device is blocking the drain-source voltage, most of the drain-source voltage drops between drain contact 75 and electrode 85. Thus the voltage across diode 99 is much smaller than the total drain-source voltage. As such, the reverse bias breakdown voltage of the diode 99 can be much smaller than the breakdown voltage of device 90, which can result in lower switching losses and lower electromagnetic interference (EMI) during switching, as compared to the case where a higher voltage diode is connected across the entire device.

FIG. 10C is a plan view of a device 90′ which is similar to device 90 of FIGS. 10A and 10B but includes several modifications. As seen in FIG. 10B, in device 90, electrode 85 extends across the entire width of the device. However, in device 90′ of FIG. 10C, electrode 85 is replaced with a plurality of electrodes 85′ along the width of the device. The sum of the widths of all of the electrodes 85′ is smaller than the gate width W_(gate) of the device 90′. As seen in FIG. 10C, each of the electrodes 85′ has a diode 99 connected between electrode 77 and the electrode 85′. Alternatively, a single diode 99 could be connected to one of the electrodes 85′, and the electrodes 85′ could all be electrically connected to one another (not shown).

FIG. 10D is a cross-sectional view of a device 90″ which is similar to device 90 of FIGS. 10A and 10B but includes several modifications. As seen in FIG. 10D, device 90″ includes a contact 85′ in place of the diode 99 and electrode 85 that were included in device 90. Contact 85′ is connected to or is part of field plate 79, and directly contacts the upper surface of the III-N materials, forming a Schottky contact to the III-N materials. Hence, with this configuration, the diode between electrode 77 and the 2DEG 19 is integrated into the device rather than being provided as an external component.

As stated earlier, III-N layers 11 and 12 have different compositions from one another. The compositions are selected such that the second III-N layer 12 has a larger bandgap than the first III-N layer 11, which helps enable the formation of 2DEG 19. As an example, III-N layer 11 can be GaN and III-N layer 12 can be AlGaN or AlInGaN, whereas layer 12 can be n-doped or can contain no significant concentration of doping impurities. In the case that layer 12 is undoped, the induced 2DEG results from the difference in polarization fields between layers 11 and 12.

Substrate 10 can be any suitable substrate upon which III-N layers 11 and 12 can be formed, for example silicon carbide (SiC), silicon, sapphire, GaN, AlN, or any other suitable substrate upon which III-N devices can be formed. In some implementations, a III-N buffer layer (not shown) such as AlGaN or AlN is included between substrate 10 and semiconductor layer 11 to minimize material defects in layers 11 and 12.

A method of forming the device of FIG. 8 is illustrated in FIGS. 11-20. The same method can be used to form the implementations illustrated in FIGS. 5-7, 9-10, and 21-24, provided that additional steps for adding additional features included in these implementations are also performed. Referring to FIG. 11, III-N material layers 11 and 12 are formed on substrate 10, for example by metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). Insulator layer 22, formed over the III-N material layers 11 and 12, is then deposited by methods such as MOCVD, plasma enhanced chemical vapor deposition (PECVD), or low pressure chemical vapor deposition (LPCVD). Next, as seen in FIG. 12, a recess is formed in the gate region of the device. The recess, which can be formed using conventional lithographical and etching techniques, is achieved by etching through the insulator layer 22, and optionally into the III-N material layers. The recess may optionally extend through the 2DEG channel 19 in the III-N material layers.

Referring to FIG. 13, a gate insulator layer 87, which for example may be formed of or include aluminum oxide, silicon dioxide, silicon nitride, hafnium oxide, and/or another wide bandgap insulator, is then deposited conformally in the recess and over the upper surface of the device. Next, as seen in FIG. 14, source and drain contacts 74 and 75, respectively, are formed. The source and drain contacts are in electrical contact with the 2DEG 19 induced in the III-N material layers. Source and drain contacts 74 and 75, respectively, can be formed in a number of ways. For example, a metal or combination of metals can be deposited, for example by evaporation, sputtering, or CVD, in ohmic contact regions 86 (shown in FIG. 8) upon the surface of layer 12, followed by a thermal anneal which results in the deposited metal forming a metallic alloy with the underlying semiconductor material. Alternatively, n-type dopants can be ion implanted into ohmic regions 86, followed by a metal deposition by evaporation, sputtering, or CVD, atop this region. Or the material in ohmic contact regions 86 can be etched away, n-type material can be regrown in this region by MOCVD or MBE, and metal can then be deposited atop this region. In an alternative implementation, the source and drain contacts are formed prior to etching the recess in the gate region.

Next, as illustrated in FIG. 15, a gate 88 is deposited conformally on the gate insulator 87 and is at least partially in the gate region 81 (labeled in FIG. 8) of the device. The gate 88 includes a main gate portion which is in the recess, as well as an extending portion 89 that is outside the recess, is over the insulator layer 22 (and also over gate insulator 87), and extends towards the drain contact 75. The extending portion 89 functions as a gate-connected field plate. Referring to FIG. 16, gate insulator 87 is then etched using the gate metal 88 as a mask, resulting in the removal of gate insulator layer 87 everywhere other than directly beneath the gate and beneath extending portion 89. The etch may be performed using an etch chemistry that etches the material of gate insulator layer 87 without substantially etching the material of gate metal 88 or of insulator layer 22.

Next, as seen in FIG. 17, the additional dielectric layer 21 and electrode-defining layer 33 are each deposited over insulator layer 22, for example by PECVD, sputtering, or evaporation. A recess 17 is then formed as follows. Referring to FIG. 18, the surface of electrode-defining layer 33 on either side of the recess is covered with a masking material such as photoresist (not shown), and the electrode-defining layer 33 is etched to form recess 17, for example by reactive ion etching RIE or inductively coupled plasma (ICP) etching. Additional dielectric layer 21 can be formed of a material that is not substantially etched by the etch procedure used to etch the recess in the electrode-defining layer 33. In such cases, the additional dielectric layer 21 functions as an etch stop layer, ensuring that the underlying insulator layer 22 is not damaged by the etch.

Referring to FIG. 19, after etching the recess 17 through the entire thickness of the electrode-defining layer 33, the portion of the additional dielectric layer 21 which is adjacent to the recess 17 is then removed, for example by performing an etch which etches the material of the additional dielectric layer 21 but does not etch the material of electrode-defining layer 33 or insulator layer 22. For example, when layers 33 and 22 are both SiN_(x), and layer 21 is AlN, the portion of layer 21 adjacent to the recess 17 in electrode-defining layer 33 can be chemically etched in a base, such as a photoresist developer.

Next, as illustrated in FIG. 20, electrode 79 is deposited conformally in the recess, for example by evaporation, sputtering, or CVD. Finally, portion 71 (shown in FIG. 8) of the field plate which connects the source contact 74 to the remainder of the field plate is formed, resulting in the transistor of FIG. 8. Alternatively, portion 71 may be formed in the same step as electrode 79.

Another implementation of a III-Nitride device 100 is shown in FIGS. 21A and 21B, where FIG. 21A is a cross-sectional view of device 100, and FIG. 21B is a circuit schematic diagram of device 100 connected to an inductive load 113. Device 100 is configured to operate as a half bridge and is operable to switch voltages across inductive load 113. Device 100 includes switches 111 and 112. Switches 111 and 112 are each similar to transistor 70 of FIG. 8, except that switch 111 lacks its own drain contact. Instead, source contact 104 of switch 112 also serves as the drain contact of switch 111. Alternatively, switches 111 and 112 could be provided as any of the enhancement-mode devices shown in FIGS. 5-7 and 9-10, preferably with the source contact of switch 112 and the drain contact of switch 111 formed as a single contact, as in FIG. 21A.

Referring to FIG. 21A, III-Nitride device 100 includes a substrate 10 (although the substrate is optional), a III-Nitride material structure including III-N layers 11 and 12 on the substrate 10, a 2DEG channel 19 in the III-Nitride material structure, an insulator layer 22 on the III-Nitride material structure, an additional dielectric layer 21 on the insulator layer 22, and an electrode-defining layer 33 on the additional dielectric layer 21. In some implementations, additional dielectric layer 21 and insulator layer 22 are optional and may be omitted (not shown). Device 100 also includes a first source contact 94, a second source contact 104, a drain contact 105, a first gate electrode 98 formed on a first gate insulator 97, and a second gate electrode 108 formed on a second gate insulator 107. The first source contact 94 and the first gate electrode 98 serve as the source and gate, respectively, of switch 111. The second gate electrode 108 and the drain contact 105 serve as the gate and drain, respectively, of switch 112. The second source contact 104 serves as both the drain of switch 111 and the source of switch 112, and is also configured to be electrically connected to inductive load 113, as shown in FIG. 21B. The first source contact 94, the second source contact 104, and the drain contact 105 each electrically contact the 2DEG channel 19.

As in previous implementations, switches 111 and 112 each include source-connected field plates 92 and 102, respectively. Field plate 92 is electrically connected to the first source contact 94, such that field plate 92 and the first source contact 94 are part of electrode 96. Field plate 102 is electrically connected to the second source contact 104, such that field plate 102 and the second source contact 104 are part of electrode 106. Similar to the field plate 79 of the transistor 70 in FIG. 8, field plate 92 is at least partially in a recess formed in electrode-defining layer 33 between the first gate electrode 98 and the second source contact 104, and field plate 102 is at least partially in a recess formed in electrode-defining layer 33 between the second gate electrode 108 and the drain contact 105.

Also as in previous implementations, gate recesses for the gates of both switches 111 and 112 are formed through the insulator layer 22 and optionally into the III-N material structure in the gate regions where gates 98 and 108 are formed, gate insulator 97 and gate electrode 98 are deposited in the first recess, and gate insulator 107 and gate electrode 108 are deposited in the second recess. As seen in FIG. 21A, the recesses containing gate electrodes 98 and 108 can be formed through the 2DEG channel 19. The first recess can be formed at least deep enough that when 0V is applied to the first gate electrode 98 relative to the first source contact 94, the device channel in the gate region of switch 111 is depleted of charge, and switch 111 is in the OFF state, but the device channel in the gate region becomes readily conductive when a sufficiently positive voltage is applied to the first gate electrode 98 relative to the first source contact 94. The second recess can be formed at least deep enough that when 0V is applied to the second gate electrode 108 relative to the second source contact 104, the device channel in the gate region of switch 112 is depleted of charge, and switch 112 is in the OFF state, but the device channel in the gate region becomes readily conductive when a sufficiently positive voltage is applied to the second gate electrode 108 relative to the second source contact 104.

Also similar to previously described implementations, in device 100 of FIG. 21A, gate electrodes 98 and 108 can each include a main gate portion and an extending portion. The main gate portion is the portion at the bottom of the recess, and the extending portion is outside the recess and extends from the main gate portion towards the drain contact. The extending portions of gate electrodes 98 and 108, which are over the upper surface of the III-N material structure (layers 11 and 12) and function as gate-connected field plates, can have a larger separation from the 2DEG channel 19 than the portions 93 and 103 of the of source-connected field plates 92 and 102, respectively. As shown, portions 93 and 103 are the portions of field plates 92 and 102, respectively, which are at the bottom of the respective recesses in electrode-defining layer 33.

Although not shown in FIG. 21A, switches 111 and 112 may each also include additional features shown in FIGS. 10A and 10B. For example, each of switches 111 and 112 can include a diode having a substantially smaller reverse bias breakdown voltage than that of the switches 111 and 112. The diodes are configured to stabilize switches 111 and 112 during reverse conduction. As in FIG. 10A, switch 111 and/or switch 112 can further include an additional electrode contacting the 2DEG 19 between the gate electrode and drain contact of the respective switch. Opposite ends of a diode are connected to the source contact and to the additional electrode. As in FIG. 10A, the anode of the diode is electrically connected to the source contact, and the cathode is electrically connected to the additional electrode. As also shown in FIG. 10A, the anode of the diode may be electrically connected directly to the source-connected field plate. Alternatively, the anode of the diode could be electrically connected directly to the source contact 94 or 104, or to a source bus which is connected to multiple source fingers. In the configuration where the anode of the diode is electrically connected directly to the source-connected field plate, when switch 111 or 112 is in reverse conduction mode, with the drain contact biased at a slightly lower voltage than the source contact and the gate biased below the device threshold voltage relative to the source contact, current flows from the source contact into the source-connected field plate, then through the diode into the additional electrode, and then through 2DEG 19 from the additional electrode to the drain contact. In the alternate configuration where the anode of the diode is electrically connected directly to the source contact 94 or 104 or to a source bus which is connected to multiple source fingers, the current flows directly from the source contact into the diode without flowing into the source-connected field plate. When switch 111 or 112 is biased with a large positive voltage on its drain contact relative to its source contact and with its gate below the device threshold voltage relative to its source contact, such that the device is blocking the drain-source voltage, most of the drain-source voltage drops between its drain contact and the additional electrode. Thus the voltage across the diode is much smaller than the total drain-source voltage. As such, the reverse bias breakdown voltage of the diode can be much smaller than the breakdown voltage of the switch 111 or 112 to which the diode is connected, which can result in lower switching losses and lower electromagnetic interference (EMI) during switching, as compared to the case where a higher voltage diode is connected across the entire switch. In one implementation, the reverse bias breakdown voltage of the diode is less than 0.5 times the breakdown voltage of the switch 111 or 112 to which the diode is connected.

Another implementation of a III-Nitride device 120 is shown in FIG. 22. Device 120 is configured to operate as a bidirectional switch, sometimes also referred to as a quadrant switch. Similar to other devices described herein, device 120 includes a substrate 10 (although the substrate is optional), a III-Nitride material structure including III-N layers 11 and 12 on the substrate 10, a 2DEG channel 19 in the III-Nitride material structure, an insulator layer 22 on the III-Nitride material structure, an additional dielectric layer 21 on the insulator layer 22, and an electrode-defining layer 33 on the additional dielectric layer 21. In some implementations, additional dielectric layer 21 and insulator layer 22 are optional and may be omitted (not shown). Device 120 also includes a first source contact 124, a second source contact 134, a first gate electrode 128 formed on a first gate insulator 127, and a second gate electrode 138 formed on a second gate insulator 137. The first source contact 124 and the second source contact 134 each electrically contact the 2DEG channel 19.

As in previous implementations, device 120 also includes source-connected field plates 122 and 132. Field plate 122 is electrically connected to the first source contact 124, such that field plate 122 and the first source contact 124 are part of electrode 126. Field plate 132 is electrically connected to the second source contact 134, such that field plate 132 and the second source contact 134 are part of electrode 136. Similar to the field plate 79 of the transistor 70 in FIG. 8, field plate 122 is at least partially in a first recess formed in electrode-defining layer 33 between the first and second gate electrodes 128 and 138, respectively, and field plate 132 is at least partially in a second recess formed in electrode-defining layer 33 between the first and second gate electrodes 128 and 138, respectively.

Also as in previous implementations, gate recesses for both gates 128 and 138 are formed through the insulator layer 22 and optionally into the III-N material structure in the gate regions where gates 128 and 138 are formed, gate insulator 127 and gate electrode 128 are deposited in the first recess, and gate insulator 137 and gate electrode 138 are deposited in the second recess. As seen in FIG. 22, the recesses containing gate electrodes 128 and 138 can be formed through the 2DEG channel 19. The first gate recess can be formed at least deep enough that when 0V is applied to the first gate electrode 128 relative to the first source contact 124 and the second source contact 134 is biased at a higher voltage than the first source contact 124, the device channel in the gate region corresponding to gate 128 is depleted of charge, and the bidirectional switch is in the OFF state, but the device channel in the gate region corresponding to gate 128 becomes readily conductive when a sufficiently positive voltage is applied to the first gate electrode 128 relative to the first source contact 124 while the second source contact 134 is still biased at a higher voltage than the first source contact 124. The second gate recess can be formed at least deep enough that when 0V is applied to the second gate electrode 138 relative to the second source contact 134 and the second source contact 134 is biased at a lower voltage than the first source contact 124, the device channel in the gate region corresponding to gate 138 is depleted of charge, and the bidirectional switch is in the OFF state, but the device channel in the gate region corresponding to gate 138 becomes readily conductive when a sufficiently positive voltage is applied to the second gate electrode 138 relative to the second source contact 134 while the second source contact 134 is still biased at a lower voltage than the first source contact 124. When gate 128 is biased OFF (i.e., below its threshold voltage relative to contact 124) and gate 138 is biased OFF (i.e., below its threshold voltage relative to contact 134), the device 120 blocks voltage between contacts 124 and 134 of either polarity (i.e., both when the voltage of contact 124 is greater than that of contact 134 and when the voltage of contact 134 is greater than that of contact 124). When gate 128 is biased ON (i.e., above its threshold voltage relative to contact 124) and gate 138 is biased ON (i.e., above its threshold voltage relative to contact 134), the device 120 can conduct current in either direction.

Also similar to previously described implementations, in device 120 of FIG. 22, gate electrodes 128 and 138 can each include a main gate portion and an extending portion. The main gate portion is the portion at the bottom of the recess, and the extending portion is outside the recess and extends from the main gate portion towards the other gate electrode. The extending portions of gate electrodes 128 and 138, which are over the upper surface of the III-N material structure (layers 11 and 12) and function as gate-connected field plates, can have a larger separation from the 2DEG channel 19 than the portions 123 and 133 of the of source-connected field plates 122 and 132, respectively. As shown, portions 123 and 133 are the portions of field plates 122 and 132, respectively, that are at the bottom of the respective recesses in electrode-defining layer 33.

Device 130 in FIG. 23 is also a bidirectional switch and is similar to device 120 of FIG. 22. However, device 130 further includes additional features that are not included in device 120. Specifically, the bidirectional switch 130 further includes diodes 148 and 149, each having a substantially smaller reverse bias breakdown voltage than the breakdown voltage of bidirectional switch 130. The diodes are configured to stabilize the device 130 during operation.

As in previously described implementations, device 130 can further include additional contacts 125 and 135 contacting the 2DEG 19 between the two gate electrodes 128 and 138. Opposite ends of a first diode 148 are connected to the first electrode 126 and to the first additional contact 125, and opposite ends of a second diode 149 are connected to the second electrode 136 and to the second additional contact 135. As illustrated in FIG. 23, the anodes of the diodes 148 and 149 are electrically connected to the electrodes 126 and 136, respectively, and the cathodes are electrically connected to the additional contacts 125 and 135, respectively. As also shown in FIG. 23, the anodes of the diodes may be electrically connected directly to the source-connected field plates. Alternatively, the anodes of the diodes could be electrically connected directly to the contacts 124 and 134, or to a source/drain bus which is connected to multiple source/drain fingers (not shown). In the configuration where the anodes of the diodes are electrically connected directly to the source-connected field plates, when the first gate electrode 128 is biased above the device threshold voltage relative to the first source contact 124, the second source contact is biased at a slightly higher voltage than the first source contact, and the second gate electrode 138 is biased below its threshold voltage relative to the second source contact 134, current flows from the second source contact 134 into the source-connected field plate 132, then through diode 149 into the additional electrode 135, and then through 2DEG 19 from the additional electrode 135 directly into the first source contact 124. In the alternate configuration where the anodes of the diodes are electrically connected directly to the source contacts 124 or 134 or to a source bus which is connected to multiple source fingers, the current flows directly from source contact 134 into diode 149 without flowing into the source-connected field plate 132. In either case, if the voltage on the second gate electrode 138 is then switched high, then the channel beneath gate electrode 138 becomes enhanced, and current flows directly from the second source contact 134 to the first source contact 124 through the 2DEG 19, without any substantial current passing through either of the diodes 148 or 149.

When the device 130 is biased in the off state, for example with a large voltage applied to the second source contact 134 relative to the first source contact 124 and with the first gate 128 biased below its threshold voltage relative to the first source contact 124, the majority of the total voltage dropped across the device is supported/blocked in the III-N material in the region between portions 123 and 133. Only a small voltage is applied across either of the diodes 148 and 149. As such, the reverse bias breakdown voltage of the diodes can be much smaller than the breakdown voltage of the bidirectional switch, which can result in lower switching losses and lower electromagnetic interference (EMI) during switching, as compared to the case where a higher voltage diode is used. In one implementation, the reverse bias breakdown voltage of the diodes is less than 0.3 times the breakdown voltage of the bidirectional switch 130. Note that when the device 130 is biased off in state described above, with a large voltage applied to the second source contact 134 relative to the first source contact 124, the device is in the off state whether the second gate electrode 138 is biased above or below its threshold voltage.

Another implementation of a III-Nitride device 140 is shown in FIG. 24. Like the devices 120 and 130 of FIGS. 22 and 23, respectively, device 140 is configured to operate as a bidirectional switch, sometimes also referred to as a quadrant switch. Similar to other devices described herein, device 140 includes a substrate 10 (although the substrate is optional), a III-Nitride material structure including III-N layers 11 and 12 on the substrate 10, a 2DEG channel 19 in the III-Nitride material structure, an insulator layer 22 on the III-Nitride material structure, an additional dielectric layer 21 on the insulator layer 22, and an electrode-defining layer 33 on the additional dielectric layer 21. In some implementations, additional dielectric layer 21 and insulator layer 22 are optional and may be omitted (not shown). Device 140 also includes a source contact 144, a first drain contact 155, a second drain contact 165, a first gate electrode 168 which is formed on a first gate insulator 167 and is between the source contact 144 and the first drain contact 155, and a second gate electrode 178 which is formed on a second gate insulator 177 and is between the source contact 144 and the second drain contact 165. The source contact 144, the first drain contact 155, and the second drain contact 155 each electrically contact the 2DEG channel 19.

As seen in FIG. 24, device 140 also includes field plates 142 and 152 which are both connected to source contact 144 and extend in opposite directions from one another, with field plate 142 extending towards the first drain contact 155 and field plate 152 extending towards the first drain contact 165. As such, source contact 144, field plate 142, and field plate 152 are all provided as a single electrode 146. Similar to the field plate 79 of the transistor 70 in FIG. 8, field plate 142 is at least partially in a first recess formed in electrode-defining layer 33 between the first gate electrode 168 and the first drain contact 155, and field plate 152 is at least partially in a second recess formed in electrode-defining layer 33 between the second gate electrode 178 and the second drain contact 165.

Also as in previous implementations, gate recesses for both gates 168 and 178 are formed through the insulator layer 22 and optionally into the III-N material structure in the gate regions where gates 168 and 178 are formed, gate insulator 167 and gate electrode 168 are deposited in the first recess, and gate insulator 177 and gate electrode 178 are deposited in the second recess. As seen in FIG. 24, the recesses containing gate electrodes 178 and 188 can be formed through the 2DEG channel 19. The first gate recess can be formed at least deep enough that when 0V is applied to the first gate electrode 168 relative to the source contact 144 and the first drain contact 155 is biased at a higher voltage than the second drain contact 165, the device channel in the gate region corresponding to gate 168 is depleted of charge, and the bidirectional switch is in the OFF state, but the device channel in the gate region corresponding to gate 168 becomes readily conductive when a sufficiently positive voltage is applied to the first gate electrode 168 relative to the source contact 144 while the first drain contact 155 is still at a higher voltage than the second drain contact 165. The second gate recess can be formed at least deep enough that when 0V is applied to the second gate electrode 178 relative to the source contact 144 and the second drain contact 165 is biased at a higher voltage than the first drain contact 155, the device channel in the gate region corresponding to gate 178 is depleted of charge, and the bidirectional switch is in the OFF state, but the device channel in the gate region corresponding to gate 178 becomes readily conductive when a sufficiently positive voltage is applied to the second gate electrode 178 relative to the source contact 144 while the second drain contact 165 is still at a higher voltage than the first drain contact 155. When gate 168 is biased OFF (i.e., below its threshold voltage relative to source contact 144) and gate 178 is biased OFF (i.e., below its threshold voltage relative to source contact 144), the device 140 blocks voltage between drain contacts 155 and 165 of either polarity (i.e., both when the voltage of drain contact 155 is greater than that of drain contact 165 and when the voltage of drain contact 165 is greater than that of drain contact 155). When gate 168 is biased ON (i.e., above its threshold voltage relative to source contact 144) and gate 178 is biased ON (i.e., above its threshold voltage relative to source contact 144), the device 140 can conduct current in either direction.

Also similar to previously described implementations, in device 140 of FIG. 24, gate electrodes 168 and 178 can each include a main gate portion and an extending portion. The main gate portion is the portion at the bottom of the recess, and the extending portion is outside the recess and extends from the main gate portion away from the source contact 144. The extending portions of gate electrodes 168 and 178, which are over the upper surface of the III-N material structure (layers 11 and 12) and function as gate-connected field plates, can have a larger separation from the 2DEG channel 19 than the portions 143 and 153 of the of source-connected field plates 142 and 152, respectively. As shown, portions 143 and 153 are the portions of field plates 142 and 152, respectively, that are at the bottom of the respective recesses in electrode-defining layer 33.

As further illustrated in FIG. 24, the bidirectional switch 140 also includes diodes 158 and 159, each having a substantially smaller reverse bias breakdown voltage than the breakdown voltage of bidirectional switch 140. The diodes are configured to stabilize the device 140 during operation.

As in previously described implementations, device 140 can further include additional contacts 165 and 175 contacting the 2DEG 19. Opposite ends of the first diode 158 are connected to the electrode 146 and to the first additional contact 165, and opposite ends of the second diode 159 are connected to the electrode 146 and to the second additional contact 175. As illustrated in FIG. 24, the anodes of the diodes 158 and 159 are electrically connected to electrode 146, and the cathodes are electrically connected to the additional contacts 165 and 175, respectively. As also shown in FIG. 24, the anodes of the diodes may be electrically connected directly to the source-connected field plates 142 and 152. Alternatively, the anodes of the diodes could be electrically connected directly to the source contact 144, or to a source bus which is connected to multiple source fingers (not shown). In the configuration where the anodes of the diodes are electrically connected directly to the source-connected field plates, when gate electrode 168 is biased above the device threshold voltage relative to the source contact 144, the first drain contact 155 is biased at a higher voltage than the second drain contact 165, and gate electrode 178 is biased below its threshold voltage relative to the source contact 144, current flows from the first drain contact 155 through the 2DEG 19 directly into the source contact 144, then through the source contact 144 into source-connected field plate 152, then through diode 159 into electrode 175, and then through 2DEG 19 from the additional electrode 175 directly into the second drain contact 165. In the alternate configuration where the anodes of the diodes are electrically connected directly to the source contact 144 or to a source bus which is connected to multiple source fingers, the current flows directly from source contact 144 into diode 159 without flowing into the source-connected field plate 152. In either case, if the voltage on the second gate electrode 178 is then switched high, the channel beneath gate electrode 178 becomes enhanced, and current can flow directly from the first drain contact 155 to the second drain contact 165 through the 2DEG 19, without any substantial current passing through either of the diodes 158 or 159.

When the device 140 is biased in the off state, for example with a large voltage applied to the first drain contact 155 relative to the second drain contact 165 and with the first gate 168 biased below its threshold voltage relative to the source contact 144, the majority of the total voltage dropped across the device 140 is supported/blocked in the III-N material in the region between the first drain contact 155 and portion 143 of field plate 142. Only a small voltage is applied across either of the diodes 158 and 159. As such, the reverse bias breakdown voltage of the diodes can be much smaller than the breakdown voltage of the bidirectional switch, which can result in lower switching losses and lower electromagnetic interference (EMI) during switching, as compared to the case where a higher voltage diode is used. In one implementation, the reverse bias breakdown voltage of the diodes is less than 0.3 times the breakdown voltage of the bidirectional switch 130. Note that when the device 140 is biased off in state described above, with a large voltage applied to the first drain contact 155 relative to the second contact 165 and gate 168 biased below its threshold voltage relative to the source contact 144, the device is in the off state whether the second gate electrode 178 is biased above or below its threshold voltage.

While bidirectional switches 120 and 130 of FIGS. 22 and 23, respectively, each include 2 power electrodes (124 and 134) and 2 gate electrodes (128 and 138), bidirectional switch 140 shown in FIG. 24 includes 2 power electrodes (155 and 165), 2 gate electrodes (168 and 178), and an additional source electrode 144. While such a configuration may be more complicated and require a larger footprint as compared to the configurations shown in FIGS. 22 and 23, the configuration of FIG. 24 can result in increased device stability in many applications.

A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the techniques and devices described herein. Features shown in each of the implementations may be used independently or in combination with one another. Accordingly, other implementations are within the scope of the following claims. 

What is claimed is:
 1. An enhancement-mode transistor, comprising: a III-N structure including a conductive channel therein; a source contact and a drain contact, the source and drain contacts electrically contacting the conductive channel; a gate electrode positioned between the source and drain contacts; an insulator layer over the III-N structure, wherein a first recess is formed through the insulator layer in a gate region of the III-N enhancement-mode transistor, the first recess comprising a first bottom surface, and wherein the gate electrode is at least partially in the first recess; an electrode defining layer having a thickness, the electrode defining layer being over the insulator layer, wherein a second recess is formed through a portion of the electrode defining layer, the second recess comprising a second bottom surface, wherein the first bottom surface of the first recess has a first edge and a second edge, the first edge being between the source contact and the second edge, and wherein the second bottom surface of the second recess has a third edge and a fourth edge, the third edge being between the source contact and the fourth edge; and a field plate having a portion that is in the second recess, the field plate being electrically connected to the source contact, wherein the third edge of the second bottom surface is between the second edge of the first bottom surface and the drain contact.
 2. The transistor of claim 1, wherein the second recess extends through the entire thickness of the electrode defining layer.
 3. The transistor of claim 1, wherein the electrode defining layer is at least partially over the gate electrode.
 4. The transistor of claim 1, further comprising a gate insulator layer in the first recess between the gate electrode and the III-N structure.
 5. The transistor of claim 4, wherein a portion of the gate insulator layer is over the insulator layer, and the gate electrode extends over the portion of the gate insulator layer.
 6. The transistor of claim 1, further comprising an etch stop layer between the insulator layer and the electrode defining layer.
 7. The transistor of claim 6, wherein the etch stop layer is at least partially over the gate electrode.
 8. The transistor of claim 6, wherein the second recess extends through the etch stop layer.
 9. The transistor of claim 8, wherein the field plate contacts the insulator layer in the second recess.
 10. The transistor of claim 8, wherein the field plate contacts an upper surface of the insulator layer in the second recess.
 11. The transistor of claim 1, wherein the first recess extends into the III-N structure.
 12. The transistor of claim 1, wherein a width of the second recess at the top of the second recess is greater than a width of the second recess at the bottom of the second recess.
 13. A method of forming an enhancement-mode transistor, comprising: providing a III-N structure including a conductive channel therein; forming a source contact and a drain contact, the source and drain contacts electrically contacting the conductive channel; forming a gate electrode between the source and drain contacts; providing an insulator layer over the III-N structure; forming a first recess through the insulator layer in a gate region of the III-N enhancement-mode transistor, the first recess comprising a first bottom surface, wherein the gate electrode is formed at least partially in the first recess; forming an electrode defining layer having a thickness, the electrode defining layer being over the insulator layer; forming a second recess through a portion of the electrode defining layer, the second recess comprising a second bottom surface; wherein the first bottom surface of the first recess has a first edge and a second edge, the first edge being between the source contact and the second edge; the second bottom surface of the second recess has a third edge and a fourth edge, the third edge being between the source contact and the fourth edge; and forming a field plate having a portion that is in the second recess, the field plate being electrically connected to the source contact, wherein the third edge of the second bottom surface is between the second edge of the first bottom surface and the drain contact.
 14. The method of claim 13, wherein the second recess extends through the entire thickness of the electrode defining layer.
 15. The method of claim 13, wherein the electrode defining layer is formed at least partially over the gate electrode.
 16. The method of claim 13, further comprising forming a gate insulator layer in the first recess between the gate electrode and the III-N structure.
 17. The method of claim 16, wherein a portion of the gate insulator layer is formed over the insulator layer, and the gate electrode extends over the portion of the gate insulator layer.
 18. The method of claim 13, wherein the field plate contacts the insulator layer in the second recess.
 19. The method of claim 13, wherein the first recess extends into the III-N structure.
 20. An enhancement-mode transistor, comprising: a III-N structure including a conductive channel therein; a source contact and a drain contact, the source and drain contacts electrically contacting the conductive channel; a gate electrode positioned between the source and drain contacts; an insulator layer over the III-N structure, wherein a first recess is formed through the insulator layer in a gate region of the III-N enhancement-mode transistor, the first recess comprising a first bottom surface, and wherein the gate electrode is at least partially in the first recess; and an electrode defining layer having a thickness, the electrode defining layer being over the insulator layer, wherein a second recess is formed through a portion of the electrode defining layer, the second recess extending through the entire thickness of the electrode defining layer and comprising a second bottom surface; wherein the first bottom surface of the first recess has a first edge and a second edge, the first edge being between the source contact and the second edge; wherein the second bottom surface of the second recess has a third edge and a fourth edge, the third edge being between the source contact and the fourth edge; wherein the source contact includes a field plate having a portion that is in the second recess; and wherein the third edge of the second bottom surface is between the second edge of the first bottom surface and the drain contact.
 21. The transistor of claim 20, further comprising a gate insulator layer in the first recess between the gate electrode and the III-N structure.
 22. The transistor of claim 21, wherein a portion of the gate insulator layer is over the insulator layer, and the gate electrode extends over the portion of the gate insulator layer.
 23. The transistor of claim 22, wherein the field plate contacts an upper surface of the insulator layer in the second recess.
 24. A method of forming an enhancement-mode transistor, comprising: providing a III-N structure including a conductive channel therein; forming a source contact and a drain contact, the source and drain contacts electrically contacting the conductive channel; forming a gate electrode between the source and drain contacts; providing an insulator layer over the structure; forming a first recess through the insulator layer in a gate region of the III-N enhancement-mode transistor, the first recess comprising a first bottom surface, wherein the gate electrode is formed at least partially in the first recess; forming an electrode defining layer having a thickness, the electrode defining layer being over the insulator layer; and forming a second recess through a portion of the electrode defining layer, the second recess extending through the entire thickness of the electrode defining layer and comprising a second bottom surface; wherein the first bottom surface of the first recess has a first edge and a second edge, the first edge being between the source contact and the fourth edge; wherein the second bottom surface of the second recess has a third edge and a fourth edge, the third edge being between the source contact and the fourth edge; and wherein the source contact includes a field plate having a portion that is in the second recess; and wherein the third edge of the second bottom surface is between the second edge of the first bottom surface and the drain contact.
 25. The method of claim 24, further comprising forming a gate insulator layer in the first recess between the gate electrode and the III-N structure.
 26. The method of claim 25, wherein a portion of the gate insulator layer is over the insulator layer, and the gate electrode extends over the portion of the gate insulator layer.
 27. The method of claim 26, wherein the field plate contacts an upper surface of the insulator layer in the second recess. 